For a Back End Of Line Dual Damascene Trench process, trilayer lithograph stack, i.e., resist, Spin On Glass (SOG)/Under Layer (UL) where the UL is an organic material similar to resist, is being used as the conventional process. During the UL coating process, a dip of about 60 nm is formed over the wide, e.g., >/=1 um, via pattern relative to the neighboring UL top surface level. After the SOG coating, the dipping region ends up with 60 nm thicker SOG compared to the neighbor. Some Dual Damascene Trench etch recipes cannot fully remove the thick SOG over the dipping UL during the main dielectric etch step. During the next UL etch, the undercut causes the big via pattern features to float and drift during cleaning.
FIGS. 2A-2H show the conventional process steps to form an example trilayer lithograph stack.
FIG. 2A shows the beginning formation of an incoming wafer. In particular, the incoming wafer 121 includes a Cu/ultra-low K (ULK) layer 101, an ES layer 102 and an ULK layer 103.
FIG. 2B shows a resultant semiconductor device stack after an incoming wafer is subjected to a via layer resist coating. In particular, semiconductor device stack 122 includes a Cu/ULK layer 101, an ES layer 102, an ULK layer 103, and a resist layer 118.
FIG. 2C shows a resultant semiconductor device stack after a semiconductor device stack is subjected to a via layer patterning. In particular, semiconductor device stack 123 includes a Cu/ULK layer 101, an ES layer 102, an ULK layer 103, and a resist layer 118. The resist layer 118 is subjected to a via layer patterning, i.e., exposure and development with a via photomask. The via layer patterning produces a via 119 in the resist layer 118.
FIG. 2D shows a resultant semiconductor device stack after a semiconductor device stack is subjected to a via etch process. In particular, semiconductor device stack 124 includes a Cu/ULK layer 101, an ES layer 102, an ULK layer 103, and a resist layer 118. A via etch process results in a thinning of the resist layer 118 and a transfer of the via pattern 119 into the ULK layer 103. Thus, a trough 120 through both the resist layer 118 and the ULK layer 103 results from a via etch process on the semiconductor device stack 123.
FIG. 2E shows a resultant semiconductor device stack after a semiconductor device stack is subjected to an ashing/wet cleaning process. In particular, semiconductor device stack 125 includes a Cu/ULK layer 101, an ES layer 102, and an ULK layer 103. An ashing/wet cleaning process results in the resist layer 118 from FIG. 2D being removed. Thus, the trough 120 remains through the ULK layer 103 after the ashing/wet cleaning process.
FIG. 2F shows a resultant semiconductor device stack after a semiconductor device stack is subjected to an underlayer (UL) coating. In particular, semiconductor device stack 126 includes a Cu/ULK layer 101, an ES layer 102, an ULK layer 103, and an UL layer 104. The UL layer 104 is shown to fill the via 120 shown in FIG. 2E and to extend over the ULK layer 103. A significant dip 211, e.g., ˜40 nm or larger, occurs over the large, e.g., ˜1 um or larger, via 120 formed in the ULK layer 103. Such a dip 211 causes problems later in the process as described below.
FIG. 2G shows a resultant semiconductor device stack after a semiconductor device stack is subjected to a SOG coating. In particular, semiconductor device stack 127 includes a Cu/ULK layer 101, an ES layer 102, an ULK layer 103, an UL layer 104, and a SOG layer 105. The SOG layer 105 is shown to fill the dip 211 shown in FIG. 2F.
FIG. 2H shows a resultant semiconductor device stack after a semiconductor device stack is subjected to a resist coating. In particular, semiconductor device stack 128 includes a Cu/ULK layer 101, an ES layer 102, an ULK layer 103, an UL layer 104, a SOG layer 105, and a trench resist layer 201. The resist layer 201 is formed over the SOG layer 105 after a resist coating process is performed on the semiconductor device stack shown in FIG. 2G.
FIGS. 3A-3F show the conventional process steps for a trilayer lithographic stack.
FIG. 3A shows the beginning formation of a semiconductor device stack 128. In particular, semiconductor device 128 includes a Cu/ULK layer 101, an ES layer 102, a ULK layer 103, an UL layer 104, a SOG layer 105, and a trench resist layer 201. The UL layer 104 is shown to include a dip 211.
FIG. 3B shows a resultant semiconductor device stack subsequent to a SOG etch process. In particular, semiconductor device stack 207 includes a Cu/ULK layer 101, an ES layer 102, a ULK layer 103, an UL layer 104, and a SOG layer 105. The trench resist layer 201 shown in FIG. 3A is removed during a SOG etch process and a portion of the SOG is also removed producing a thinned SOG layer 105 shown in FIG. 3B.
FIG. 3C shows a resultant semiconductor device stack subsequent to an UL etch process. In particular, semiconductor device stack 208 includes a Cu/ULK layer 101, an ES layer 102, a ULK layer 103, an UL layer 104, and a SOG layer 105. A minimal amount of the SOG layer 105 shown in FIG. 3B is removed during the UL etch process.
FIG. 3D shows a resultant semiconductor device stack subsequent to an ULK etch process. In particular, semiconductor device stack 209 consists of a Cu/ULK layer 101, an ES layer 102, a ULK layer 103, and an UL layer 104. A very small portion of the SOG layer 105 from FIG. 3C remains after the ULK etch, shown in FIG. 3D as a SOG remnant 105.
Thus, because of the dip 211 produced during the underlayer coating shown in FIG. 2F the SOG layer 105 above the dip 211 is larger than would be produced without such a dip 211. The thick SOG layer 105 above the dip 211 from FIG. 3C cannot be completely removed during the ULK etch process with a conventional microloading/ULK damage minimization recipe. Alternately, the thick SOG layer 105 above the dip 211 from FIG. 3C can be removed by using etch recipes optimized for that special purpose, but use of such recipes limits options to improve other serious challenges, e.g., microloading that results in varying etch depth that depends on the pattern density, and ULK damage during ULK etch.
FIG. 3E shows a resultant semiconductor device stack subsequent to an in-situ ash process. In particular, semiconductor device 210 consists of a Cu/ULK layer 101, an ES layer 102, and a ULK layer 103. The SOG remnant 105 shown FIG. 3D prevents a thorough removal of the UL layer 104 that resides in the via in the ULK layer 103. As a result of the SOG remnant 105 shown in FIG. 3D, an in-situ ash process leaves behind UL material 104 within the ULK layer 103 via.
FIG. 3F shows a resultant semiconductor device stack subsequent to solvent cleaning process. In particular, semiconductor device 212 consists of a Cu/ULK layer 101, an ES layer 102, and a ULK layer 103. The UL layer material 104 in the ULK layer 103 via and a portion of the ES layer 102 is lifted off and floats on the wafer surface during the solvent cleaning process. Penetration and agitation of the cleaning solvent is needed to lift the UL layer material 104 and a portion of the ES layer 102, shown by the arrows surrounding the UL layer material 104 and a portion of the ES layer 102.
Thus, as can be seen from FIGS. 3A-3F a thick SOG layer, e.g., approximately 130 nm, cannot be fully removed during an ULK etch process resulting in a portion of an UL material being left behind in a ULK layer via.
Attempts have been made to relieve the dipping problem and the associated thick SOG coating. Modification of the UL or SOG coating process has been tried but had negligible improvement. A dual UL coating can planarize before SOG coating, but it is an expensive, complex, and long process. An etch process that can remove thick SOG during dielectric etch completely, but introduces ULK damage and micro-loading. Segmentations may be added inside of large features, but segmentations are not always an option due to design constraints.
Accordingly, the present teachings solve these and other problems of the prior art's SOG removal during ULK etch resulting in the prevention of an UL material being left behind in an ULK layer via.